- 邊界紹
- boundary: n. 邊界，疆界，限界 (between);(球場(chǎng))邊線 ...
- scan: vt. (-nn-) 1.細(xì)看，細(xì)察；審視。 2.〔口語 ...
- test: n. 【動(dòng)物；動(dòng)物學(xué)】(軟體類的)介殼，甲殼；【植物；植 ...
- boundary scan: 邊界掃描
- scan boundary: 邊緣掃描
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boundary scan test中文什么意思
- 邊界紹
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例句與用法
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- A plan of design for test based of boundary scan testing is introduced for this signal processing system
接著，提出了該信號(hào)處理系統(tǒng)基于邊界掃描的可測(cè)性設(shè)計(jì)方案。 - As one of the design for testability technology , boundary scan test ( bst ) fixes boundary scan cells between the device pins and core logics . thus , the bsc acts as the virtual test probe that carries out the test stimulus and captures the test response
作為一種結(jié)構(gòu)插入的可測(cè)性技術(shù),邊界掃描測(cè)試( bst )技術(shù)將邊界掃描寄存器單元安插在集成電路內(nèi)部的每個(gè)引腳上,其作用相當(dāng)于設(shè)置了施加激勵(lì)和觀測(cè)響應(yīng)的內(nèi)建虛擬探頭。 - Chapter two detailedly presents the design of the boundary scan testing system which is in accordance with ieee . 1149 . correspondingly two special - used data registers are added , one of which is the scanning chain register and the other is the child scanning chain control - register
文中第二章按照ieee . 1149標(biāo)準(zhǔn)詳細(xì)設(shè)計(jì)了邊緣掃描測(cè)試系統(tǒng)，相應(yīng)增加了兩個(gè)專用數(shù)據(jù)寄存器，其中一個(gè)為掃描鏈寄存器，一個(gè)為掃描子鏈控制寄存器。 - The majority of the test vectors are used to check the connection of the pins of the device . those vectors for connection test can be removed from the vector base for the device under test when deltascan is applied together with boundary scan test . the total vectors are therefore eliminated
測(cè)試矢量中大多數(shù)是用于測(cè)試引腳之間是否有短路或有引腳開路情況的，引入deltascan測(cè)試ic的引腳的開路和短路情況后，就可從xc5210 _ tq144的測(cè)試矢量集中去掉合并與短路，開路測(cè)試有關(guān)的測(cè)試矢量，進(jìn)一步減少了邊界掃描所需的測(cè)試矢量。 - In the logic design , the fundamentals and characteristics of ieee std . 1149 . 1 specification and usb protocol are introduced first of all . according to altera ’ s fpga cyclone , it analyzes the architecture and jtag instructions of boundary scan test ( bst ) . then the dissertation analyzes how to program cyclone device and offer the scheme of the design which is realized in verilog hdl by modelsim and quartus ii software
在接口邏輯設(shè)計(jì)中,首先分析ieee1149 . 1標(biāo)準(zhǔn)和usb協(xié)議,理解邊界掃描測(cè)試和usb數(shù)據(jù)傳輸?shù)墓ぷ鞣绞?然后針對(duì)altera公司的fpga器件cyclone ,通過分析它的邊界掃描測(cè)試結(jié)構(gòu)和各種jtag指令,研究它的編程過程和編程特點(diǎn),并提出設(shè)計(jì)方案。